1. Field of the Invention
The present invention relates to an input protecting circuit in use with a MOS semiconductor device for protecting a gate insulating film of a transistor contained in an input stage from a high voltage noise.
2. Description of the Related Art
One of the major problems in the IC device, which frequently arises after a manufactured IC chip is packaged, is a breakdown due to ESD (Electric Static Discharge). This is a gate breakdown phenomenon caused through a occurrence that when a charged object such as a human body or mechanical object makes contact with an external pin or pins of the packed IC, charges flow from the object to the inside of the IC package, and consequently a high voltage is applied to the gate of the MOS transistor in the input state of the IC semiconductor circuit, and possibly damages the gate of the transistor. To protect the gate from excessive stress, some measure must be taken to clamp the voltage applied to the gate.
A typical measure thus far taken is to place protecting element 62 of a diode or a bipolar transistor, for example, near and in connection with input pad 61 connected to an external pin (not shown) of an IC package, as shown in FIG. 1. Provision of protecting element 62 clamps an excessively high or surge voltage applied to input pad 61, and inhibits the surge voltage from traveling and reaching MO transistor 63 in the input stage. Thus, the protecting element is located near the input pad. The reason for this is that the protecting element may operate as a latch-up generating source, for example, to adversely influence the internal circuit, and hence the protecting element must be located apart from the internal circuit to such an extent that it has little adverse effect on the internal circuit.
For the thick gate oxide film of the MOS transistor 63, the above protecting circuit satisfactorily functions. In a recent trend of thinner oxide films, the conventional protecting circuit is frequently nonfunctional. This will be described in detail by using a specific example. In the circuit of FIG. 1, let us consider a case that protecting element 62 is an aluminum field transistor (equivalent to a bipolar transistor) of which the channel width is 500 .mu.m, and the interval between the source and drain diffusion regions, 2.4 .mu.m, and the gate oxide film of MOS transistor 63 in the input stage is 250 .ANG. thick. In this case, a breakdown voltage at the pn junction of this transistor is approximately 15 V. If it is clamped at approximately 15 V, an electric field applied to the gate of the MOS transistor in the input stage is 6 MV/cm at most. There is no danger that such an electric field will break down the gate.
The EIAJ Standard for the ESD evaluation method has gradually been replaced by the MIL Standard. The evaluation conditions (100 pF, 1.5 kilo ohms) under the MIL Standard was applied for evaluating the conventional protecting circuit. In the evaluation, when a voltage of approximately .+-.1400 V was applied to input pad 51, gate breakdown was observed. When the applied voltage is positive in polarity, the electric field applied to the gate is 6 MV/cm. When it is negative, the applied electric field is much smaller than the former and gate breakdown cannot occur. Nevertheless, gate breakdown was actually observed for both the positive and negative voltages applied. No one has exactly explicated the cause of this phenomenon. We reason that the inductance component involved the probably makes a great contribution to the gate breakdown. This will be described below. Normally, aluminum wire of several mm in length exists ranging from the protecting element placed near the input pad inside the IC to the internal circuit. The wire has inductance L of approximately several tens nH.
It is assumed now that an ESD stress is applied to an external pin (not shown), and a high voltage noise as shown in FIG. 2(A) is applied to the input pad. Under this condition, a potential near the wire connecting to protecting element 62 is clamped at the breakdown voltage Vbk of protecting element 62, as shown in FIG. 2(B). When the potential stepwise or abruptly changes in this way, inductance L acts so that the potential of the wire near the gate of MOS transistor 63 oscillates as shown in FIG. 2(C). During the oscillation, the potential applied to the gate instantaneously exceeding the clamped voltage by the protecting element repeatedly appears. The excess potentials repeatedly cause stress in the gate oxide film, finally resulting in gate breakdown.